EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 134

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

5–18
Stratix IV Device Handbook Volume 1
Clock Source Control for PLLs
The PLL can remain locked independent of the clkena signals because the
loop-related counters are not affected. This feature is useful for applications that
require a low-power or sleep mode. The clkena signal can also disable clock outputs if
the system is not tolerant of frequency over-shoot during resynchronization.
The clock input to Stratix IV PLLs comes from clock input multiplexers. The clock
multiplexer inputs come from dedicated clock input pins, PLLs through the GCLK
and RCLK networks, or from dedicated connections between adjacent top/bottom
and left/right PLLs. The clock input sources to top/bottom and left/right PLLs (L2,
L3, T1, T2, B1, B2, R2, and R3) are shown in
input sources to left and right PLLs (L1, L4, R1, and R4) are shown in
The multiplexer select lines are only set in the configuration file (.sof or .pof). After
programmed, this block cannot be changed without loading a new configuration file
(.sof or .pof). The Quartus II software automatically sets the multiplexer select signals
depending on the clock sources selected in the design.
Figure 5–16. Clock Input Multiplexer Logic for L2, L3, T1, T2, B1, B2, R2, and R3 PLLs
Notes to
(1) When the device is operating in user mode, input clock multiplexing is controlled through a configuration file (.sof
(2) n=0 for L2 and L3 PLLs; n=4 for B1 and B2 PLLs; n=8 for R2 and R3 PLLs, and n=12 for T1 and T2 PLLs.
(3) You can drive the GCLK or RCLK input using an output from another PLL, a pin-driven GCLK or RCLK, or through a
Figure 5–17. Clock Input Multiplexer Logic for L1, L4, R1, and R4 PLLs
Notes to
(1) Dedicated clock input pins to the PLLs are L1, L4, R1, and R4, respectively. For example, PLL_L1_CLK is the
(2) You can drive the GCLK or RCLK input using an output from another PLL, a pin-driven GCLK or RCLK, or through a
(3) The center clock pins can feed the corner PLLs on the same side directly through a dedicated path. However, these
or .pof) only and cannot be dynamically controlled.
clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
GCLK or RCLK. An internally generated global signal or general purpose I/O pin cannot drive the PLL.
dedicated clock input for PLL_L1.
clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
GCLK or RCLK. An internally generated global signal or general purpose I/O pin cannot drive the PLL.
paths may not be fully compensated.
Figure
Figure
GCLK / RCLK input (3)
5–16:
5–17:
Adjacent PLL output
clk[n+3..n] (2)
PLL_<L1/L4/R1/R4>_CLK (1)
CLK[0..3] or CLK[8..11] (3)
GCLK/RCLK (2)
4
4
4
4
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Figure
(1)
(1)
5–16; the corresponding clock
inclk0
inclk1
Clock Networks in Stratix IV Devices
February 2011 Altera Corporation
To the clock
switchover block
inclk0
inclk1
Figure
5–17.