EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 554

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–110
Table 1–40. Functional Modes for the Stratix IV GX and GT Devices
Table 1–41. Functional Modes for the Stratix IV GT Devices (Part 1 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
Basic Single Width
Basic Double Width
PCIe
XAUI
GIGE
Serial RapidIO
SONET/SDH
SDI
(OIF) CEI PHY Interface
Basic Single Width
Basic Double Width
Basic (PMA-Direct)
single-width
Basic (PMA-Direct)
double-width
XAUI
GIGE
Functional Mode
Functional Mode
Functional Modes
f
Dynamic Reconfiguration of the CMU Channel Analog Controls
For the dynamic reconfiguration capabilities of the CMU channels in Basic
(PMA Direct) ×1/×N configurations, refer to the
Devices
Table 1–40
Stratix IV GX and GT devices using the ALTGX MegaWizard Plug-In Manager.
Table 1–41
Stratix IV GT devices using the ALTGX MegaWizard Plug-In Manager.
600 Mbps to 3.75 Gbps
1 Gbps to 8.5 Gbps
■
■
3.125 Gbps up to HiGig at 3.75 Gbps
1.25 Gbps
■
■
■
■
■
■
■
>4.976 Gbps to 6.375 Gbps
600 Mbps to 3.75 Gbps
1.0 to 11.3 Gbps
600 Mbps to 3.25 Gbps
1.0 to 6.5 Gbps
3.125 Gbps up to HiGig at 3.75 Gbps
1.25 Gbps
chapter.
Gen1 at 2.5 Gbps
Gen2 at 5 Gbps
1.25 Gbps
2.5 Gbps
3.125 Gbps
OC-12
OC-48
HD at 1.485/1.4835 Gbps
3G at 2.97/2.967 Gbps
lists the transceiver functional modes you can use to configure the
lists the transceiver functional modes you can use to configure the
Data Rate
Data Rate
“Basic Single-Width Mode Configurations” on
page 1–113
“Basic Double-Width Mode Configurations” on
page 1–117
“PCIe Mode Configurations” on page 1–128
“XAUI Mode Datapath” on page 1–157
“GIGE Mode Datapath” on page 1–167
“Serial RapidIO Mode” on page 1–182
“SONET/SDH Frame Structure” on page 1–172
“SDI Mode Datapath” on page 1–180
“(OIF) CEI PHY Interface Mode Datapath” on
page 1–182
“Basic Single-Width Mode Configurations” on
page 1–113
“Basic Double-Width Mode Configurations” on
page 1–117
“Basic (PMA Direct) ×1 Configuration” on
page 1–189
“Basic (PMA Direct) ×N Configuration” on
page 1–189
“XAUI Mode Datapath” on page 1–157
“GIGE Mode Datapath” on page 1–167
Chapter 1: Transceiver Architecture in Stratix IV Devices
Dynamic Reconfiguration in Stratix IV
Refer To
Refer To
February 2011 Altera Corporation
Transceiver Block Architecture