EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 313

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
February 2011 Altera Corporation
1
For LVDS receivers, the Quartus II software provides an RSKM report showing the
SW, TUI, and RSKM values for non-DPA mode. You can generate the RSKM report by
executing the report_RSKM command in the TimeQuest Timing Analyzer. You can
find the RSKM report in the Quartus II compilation report under the TimeQuest
Timing Analyzer section.
In order to obtain the RSKM value, you must assign an appropriate input delay to the
LVDS receiver through the TimeQuest Timing Analyzer constraints menu.
For assigning input delay, follow these steps:
1. The Quartus II TimeQuest Timing Analyzer GUI has many options for setting the
Figure 8–28. Selection of Constraint Menu in TimeQuest Timing Analyzer
constraints and analyzing the design.
the Constraints menu. For setting input delay, you must select the Set Input Delay
option.
Figure 8–28
shows various commands on
Stratix IV Device Handbook Volume 1
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