EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 38
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
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ALTERA21
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2–2
Figure 2–1. Stratix IV LAB Structure and Interconnects
Stratix IV Device Handbook Volume 1
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
R20
R4
Figure 2–1
The LAB of the Stratix IV device has a derivative called memory LAB (MLAB), which
adds look-up table (LUT)-based SRAM capability to the LAB, as shown in
The MLAB supports a maximum of 640 bits of simple dual-port static random access
memory (SRAM). You can configure each ALM in an MLAB as either a 64 × 1 or a
32 × 2 block, resulting in a configuration of either a 64 × 10 or a 32 × 20 simple
dual-port SRAM block. MLAB and LAB blocks always coexist as pairs in all Stratix IV
families. MLAB is a superset of the LAB and includes all LAB features.
Local Interconnect
shows the Stratix IV LAB structure and interconnects.
LAB
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
C4
from Either Side by Columns & LABs,
C12
Local Interconnect is Driven
& from Above by Rows
Row Interconnects of
Variable Speed & Length
MLAB
ALMs
Column Interconnects of
Variable Speed & Length
February 2011 Altera Corporation
Logic Array Blocks
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Figure
2–2.
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