EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 787

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Channels in Basic (PMA Direct) Configurations
February 2011 Altera Corporation
Basic (PMA Direct) ×N Configurations
When you configure a transceiver channel in Basic (PMA Direct) ×N configuration,
you can enable the Quartus II software to use the ×N lines to provide clocks to the
transmitter channels, as shown in
The following are the possible sources driving the ×N clock lines:
■
■
Channel Placement in a Basic (PMA Direct) ×N Mode Instance
If you compile a design with a transceiver instance configured in Basic (PMA Direct)
xN mode, the Quartus II software, by default, places these channels contiguously.
You can force the placement of the transceiver channels across multiple transceiver
blocks on the same side of the device by assigning pins to the transmitter and receiver
serial ports.
The logical channel 0 of the Basic (PMA Direct) ×N mode instance does not have to be
assigned to the physical channel 0 of a transceiver block. The logical channel 0 of an
instance with multiple channels is tx_dataout[0] or rx_datain[0], which are the
serial transmit and receive ports provided by the ALTGX MegaWizard Plug-In
Manager. When you assign pins, you are not required to assign tx_dataout[0] to the
location of physical channel 0 in the transceiver block to compile your design.
This is not the case if you have a PCIe ×4 configuration where tx_dataout[0]and
rx_datain[0] must be assigned to physical channel 0 of the transceiver block.
The CMU0 central divider within the CMU0 channel. Only the CMU0 clock divider
block can drive the ×N clock lines. Either the CMU0 PLL or CMU1 PLL can drive the
central clock divider block.
f
The ATX PLL block.
To understand the input clock connections to the central clock divider
block, refer to the “CMU0 Channel” section in the
Stratix IV Devices
chapter.
Figure
3–18.
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver Architecture in
3–33