EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 1053

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EP4SGX360FH29C3N

Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Example 1: Fibre Channel Protocol Application
Figure 2–17. Transceiver—FPGA Fabric Interface
February 2011 Altera Corporation
processing
processing
processing
processing
processing
logic
data
data
logic
data
logic
Channels 0, 1, and 2 have separate rx_digitalreset, rx_analogreset, and
tx_digitalreset signals.
transceiver instances and the FPGA fabric.
logic
logic
Transmitter Side Logic
data
data
Transmitter Side Logic
Receiver Side Logic
Transmitter Side Logic
Receiver Side Logic
User Logic
decoder
8B/10B
encoder
decoder
encoder
8B/10B
8B/10B
encoder
8B/10B
8B/10B
Reset Control
for CMU PLL
Control
Reset
Control
Control
Logic
Reset
Reset
Logic
Logic
rx_freqlocked
tx_digitalreset
rx_digitalreset
rx_analogreset
rx_patterndetect
rx_syncstatus
rx_dataout
tx_digitalreset
tx_datain
tx_datain
pll_powerdown
pll_locked
rx_freqlocked
tx_digitalreset
rx_digitalreset
rx_analogreset
tx_datain
rx_patterndetect
rx_syncstatus
rx_dataout
pll_powerdown
pll_locked
Figure 2–17
Starting channel
ALTGX Instance
ALTGX Instance
Starting channel
ALTGX Instance
Starting channel
reconfig_fromgxb[16:0]
reconfig_fromgxb[16:0]
number = 8
number = 0
number = 4
Channel 2
Channel 1
Channel0
reconfig_togxb[3:0]
reconfig_togxb[3:0]
shows the interface between the three
reconfig_togxb[3:0]
reconfig_fromgxb[16:0]
Stratix IV Device Handbook Volume 3
ALTGX_RECONFIG
reconfig_fromgxb[16:0]
reconfig_fromgxb[50:34]
reconfig_fromgxb[33:17]
Instance
2–35

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