EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 626
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Quantity
Price
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
Quantity:
53
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1–182
Figure 1–148. (OIF) CEI PHY Interface Mode Datapath
Figure 1–149. Transceiver Clocking in (OIF) CEI PHY Interface Mode
Stratix IV Device Handbook Volume 2: Transceivers
tx_coreclk
rx_coreclk
FPGA
Fabric
FPGA
Fabric-Transmitter
Interface Clock
FPGA
Fabric-Receiver
Interface Clock
(OIF) CEI PHY Interface Mode Datapath
Figure 1–148
in (OIF) CEI PHY interface mode.
Figure 1–149
Serial RapidIO Mode
The RapidIO Trade Association defines a high-performance, packet-switched
interconnect standard to pass data and control information between microprocessors,
digital signal, communications, and network processors, system memories, and
peripheral devices.
Serial RapidIO physical layer specification defines three line rates:
■
■
■
Transceiver Block Clocking with the
Use central clock divider to improve
transmitter jitter option disabled
1.25 Gbps
2.5 Gbps
3.125 Gbps
rx_clkout
CMU PLL
Compensation
Compensation
tx_clkout
wrclk
RX Phase
TX Phase
FIFO
FIFO
shows the ALTGX megafunction transceiver datapath when configured
shows transceiver clocking in (OIF) CEI PHY interface mode.
rdclk
Local Clock Divider Block
Local Clock Divider Block
Local Clock Divider Block
Local Clock Divider Block
wrclk
Serializer
/2
Byte
Ch 3
Ch 2
Ch 1
Ch 0
rdclk
Serializer
Parallel Recovered Clock
Byte
Low-Speed Parallel Clock
De-
Transmitter Channel PCS
/2
Receiver Channel PCS
Chapter 1: Transceiver Architecture in Stratix IV Devices
Channel 3
Channel 2
Channel 1
Channel 0
Serializer
Receiver Channel PMA
Transmitter Channel PMA
De-
Serializer
Divider
Clock
Local
February 2011 Altera Corporation
CDR
High-Speed Serial Clock
Transceiver Block Architecture
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