EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 189

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
Figure 6–16. Number of I/Os in Each Bank in EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the 1517-Pin
FineLine BGA Package
Note to
(1) There are two additional PMA-only transceiver channels in each transceiver bank.
I/O Structure
February 2011 Altera Corporation
Figure
6–16:
The I/O element (IOE) in Stratix IV devices contain a bidirectional I/O buffer and I/O
registers to support a complete embedded bidirectional single data rate or DDR
transfer. The IOEs are located in I/O blocks around the periphery of the Stratix IV
device. There are up to four IOEs per row I/O block and four IOEs per column I/O
block. The row IOEs drive row, column, or direct link interconnects. The column IOEs
drive column interconnects.
The Stratix IV bidirectional IOE also supports the following features:
■
■
■
■
■
■
■
■
(Note 1)
Number
4 (1)
4 (1)
4 (1)
of I/Os
43
22
23
46
Programmable input delay
Programmable output-current strength
Programmable slew rate
Programmable output delay
Programmable bus-hold
Programmable pull-up resistor
Open-drain output
On-chip series termination with calibration
Name
GXBL2
Bank 1A
Bank 1C
Bank 2C
Bank 2A
GXBL1
GXBL0
Bank
Bank
Bank
Bank
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G5
Bank 6A
Bank 6C
Bank 5C
Bank 5A
GXBR0
GXBR2
GXBR1
Bank
Bank
Bank
Name
Bank
Number
of I/Os
Stratix IV Device Handbook Volume 1
4 (1)
4 (1)
4 (1)
44
23
23
46
6–17