EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 777

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Channels Configured in Protocol Functional Modes
Figure 3–11. Basic ×8/PCIe ×8 Functional Mode Configuration when Combining Channels (CMU PLL)
Notes to
(1) You can configure this channel in Basic (PMA Direct) single-width or double-width mode.
(2) You can configure this channel only in Basic (PMA Direct) single-width mode.
(3) The red lines represent the ×N top clock line, the blue lines represent the ×4 clock line, and the black line represents the ×N bottom clock line.
(4) To simplify the illustration, only the transmitter side is shown. PCIe ×8 refers to PCIe with the sub protocol set to Gen1 ×8 and Gen2 ×8.
February 2011 Altera Corporation
Figure
3–11:
■
Figure 3–11
restrictions when using CMU PLL.
If the CMU PLL is used to generate clocks for the ×8 bonded functional mode, you
can use the CMU0 channel in the slave transceiver block only in Basic (PMA Direct)
×N mode in the single-width configuration. You can use the CMU1 channels in both
the master and slave transceiver blocks in Basic (PMA Direct) ×N mode in
single-width or double-width configuration.
(Used for clock generation)
[PMA Direct] xN mode) (2)
CMU0 Channel
TX - (Basic
shows the Basic ×8 functional mode configuration for these combination
Master Transceiver Block
Slave Transceiver Block
CMU0 Channel
(Basic [PMA Direct] xN mode) (1)
(Basic [PMA Direct] xN mode) (1)
TX6 - Basic x8/
TX7 - Basic x8/
TX5 - Basic x8/
TX4 - Basic x8/
TX2 - Basic x8/
TX3 - Basic x8/
ATX PLL
TX0 - Basic x8/
TX1 - Basic x8/
PCIe x8
PCIe x8
PCIe x8
PCIe x8
PCIe x8
PCIe x8
PCIe x8
CMU1 Channel
CMU1 Channel
PCIe x8
Central Clock
Central Clock
Divider
Divider
xN Top Clock Line (3)
x4 Clock Line (3)
x4 Clock Line (3)
xN Bottom Clock Line (3)
Stratix IV Device Handbook Volume 2: Transceivers
(Note 4)
3–23