EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 634

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–190
Stratix IV Device Handbook Volume 2: Transceivers
Loopback Modes
f
f
For more information about combining multiple transceiver channels, refer to the
Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Each receiver in a receiver channel has a dedicated CDR that provides a high-speed
clock.
For more information about timing closure in Basic (PMA Direct) mode, refer to
AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional
Stratix IV GX and GT devices provide various loopback options that allow you to
verify how different functional blocks work in the transceiver channel. The available
loopback options are:
■
■
■
■
■
Serial Loopback
The serial loopback option is available for all functional modes except PCIe mode.
Figure 1–155
passes through the transmitter channel and gets looped back to the receiver channel,
bypassing the receiver buffer. The received data is available to the FPGA logic for
verification. Using this option, you can check the working for all enabled PCS and
PMA functional blocks in the transmitter and receiver channel. When you enable the
serial loopback option, the ALTGX MegaWizard Plug-In Manager provides the
rx_seriallpbken port to dynamically enable serial loopback on a channel-by-channel
basis. Set the rx_seriallpbken signal to logic high to enable serial loopback.
When serial loopback is enabled, the transmitter channel sends the data to both the
tx_dataout output port and to the receiver channel. The differential output voltage on
the tx_dataout ports is based on the selected V
received by the receiver CDR and is retimed through different clock domains. You
must provide an alignment pattern for the word aligner to enable the receiver channel
to retrieve the byte boundary.
Suppose the device is not in serial loopback mode and is receiving data from a remote
device. At this point, the receiver CDR’s recovered clock is locked to the data from
that source. If the device is placed in serial loopback mode, the data source to the
receiver changes from the remote device to local transmitter channel. This prompts
the receiver CDR to start tracking the phase of the new data source. During this time,
the receiver CDR’s recovered clock may be unstable. As the receiver PCS is running
off of this recovered clock, you must place the receiver PCS under reset by asserting
the rx_digitalreset signal during this time period.
“Serial Loopback” on page
mode
“Parallel Loopback” on page
double-width modes.
“Reverse Serial Loopback” on page
“Reverse Serial Pre-CDR Loopback” on page
“PCIe Reverse Parallel Loopback” on page
shows the datapath for serial loopback. The data from the FPGA fabric
1–190—available in all functional modes except PCIe
1–191—available in either single-width or
1–193—available in Basic mode only
Chapter 1: Transceiver Architecture in Stratix IV Devices
1–194—available in PCIe mode
OD
1–194—available in Basic mode only
settings. The looped back data is
February 2011 Altera Corporation
Transceiver Block Architecture
chapter.
Mode.