EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 281

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Locations of the I/O Banks
Locations of the I/O Banks
Figure 8–2. High-Speed Differential I/Os with DPA Locations in Stratix IV E Devices
February 2011 Altera Corporation
1
The ALTLVDS transmitter and receiver requires various clock and load enable signals
from a left or right PLL. The Quartus
when configuring the LVDS SERDES circuitry when using the PLL:
■
■
Both choices target the same physical PLL; the only difference is the additional
flexibility provided when an LVDS interface has the Use External PLL option
enabled.
Stratix IV I/Os are divided into 16 to 24 I/O banks. The dedicated circuitry that
supports high-speed differential I/Os is located in banks in the right and left side of
the device.
LVDS interface with the Use External PLL option enabled—You control the PLL
settings, such as dynamically reconfiguring the PLL to support different data
rates, dynamic phase shift, and so on. You must enable the Use External PLL
option in the ALTLVDS megafunction, using the ALTLVDS MegaWizard
Manager software. You also must instantiate an ALTPLL megafunction to generate
the various clocks and load enable signals. For more information, refer to
Interface with the Use External PLL Option Enabled” on page
LVDS interface with the Use External PLL option disabled—The Quartus II
software configures the PLL settings automatically. The software is also
responsible for generating the various clock and load enable signals based on the
input reference clock and data rate selected.
Figure 8–2
General Purpose
General Purpose
I/O and Memory
I/O and Memory
PLL
PLL
PLL
PLL
Interface
Interface
shows a high-level chip overview of the Stratix IV E device.
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
FPGA Fabric
PLL
PLL
PLL
PLL
®
II software provides the following two choices
General Purpose
General Purpose
I/O and Memory
I/O and Memory
Interface
Interface
PLL
PLL
PLL
PLL
Stratix IV Device Handbook Volume 1
8–26.
™
“LVDS
Plug-in
8–3