HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 10

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

8.2
8.3
8.4
8.5
8.6
Section 9 Direct Memory Access Controller (DMAC)
9.1
9.2
9.3
Rev. 5.00 Jan 06, 2006 page x of xx
8.1.4
8.1.5
Description of Registers.................................................................................................... 115
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
Accessing Ordinary Space ................................................................................................ 124
8.3.1
8.3.2
8.3.3
Waits between Access Cycles ........................................................................................... 128
8.4.1
8.4.2
Bus Arbitration.................................................................................................................. 131
Memory Connection Examples......................................................................................... 132
Overview........................................................................................................................... 135
9.1.1
9.1.2
9.1.3
9.1.4
Register Descriptions ........................................................................................................ 140
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
Operation .......................................................................................................................... 150
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
Register Configuration......................................................................................... 111
Address Map ........................................................................................................ 112
Bus Control Register 1 (BCR1) ........................................................................... 115
Bus Control Register 2 (BCR2) ........................................................................... 116
Wait Control Register 1 (WCR1)......................................................................... 119
Wait Control Register 2 (WCR2)......................................................................... 121
RAM Emulation Register (RAMER)................................................................... 122
Basic Timing........................................................................................................ 124
Wait State Control................................................................................................ 125
CS Assert Period Extension ................................................................................. 127
Prevention of Data Bus Conflicts......................................................................... 128
Simplification of Bus Cycle Start Detection ........................................................ 130
Features................................................................................................................ 135
Block Diagram ..................................................................................................... 137
Pin Configuration................................................................................................. 138
Register Configuration......................................................................................... 138
DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 140
DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 141
DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 142
DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 143
DMAC Operation Register (DMAOR) ................................................................ 148
DMA Transfer Flow ............................................................................................ 150
DMA Transfer Requests ...................................................................................... 152
Channel Priority ................................................................................................... 155
DMA Transfer Types........................................................................................... 158
Address Modes .................................................................................................... 159
Dual Address Mode ............................................................................................. 160
Bus Modes ........................................................................................................... 167
Relationship between Request Modes and Bus Modes by DMA Transfer
Category............................................................................................................... 168
Bus Mode and Channel Priority Order................................................................. 169
............................................ 135