HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 572

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 18 ROM (128 kB Version)
Rev. 5.00 Jan 06, 2006 page 552 of 818
REJ09B0273-0500
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is
continuously at prescribed bit rate
host to indicate end of adjustment
After bit rate adjustment, SH7050
of H'00 data transmitted by host
transmits one H'00 data byte to
Host confirms normal reception
indication (H'00), and transmits
SH7050 calculates bit rate and
SH7050 measures low period
sets value in bit rate register
SH7050 transmits one H'AA
of bit rate adjustment end
Host transfers data (H'00)
and execute reset-start
Set pins to boot mode
transmitted as an erase error, and the erase operation and subsequent operations
are halted.
After receiving H'55,
one H'55 data byte
data byte to host
Start
Figure 18.4 Boot Mode Execution Procedure
Host transmits programming control
program transferred to on-chip RAM
program sequentially in byte units
SH7050 transmits one H'AA data
number of bytes to host as verify
of programming control program
programming control program to
control program to on-chip RAM
if data has already been written,
Transfer received programming
memory data has been erased,
host as verify data (echo-back)
Check flash memory data, and
bytes (N), upper byte followed
Execute programming control
After confirming that all flash
SH7050 transmits received
SH7050 transmits received
Host transmits number
End of transmission
data (echo-back)
erase all blocks
by lower byte
byte to host
n = N?
n = 1
Yes
No
n + 1
n