HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 812

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Appendix A On-Chip Supporting Module Registers
Timer Control/Status Register (TCSR)
Note:
Bit
7
6
5
2–0
Note:
Rev. 5.00 Jan 06, 2006 page 792 of 818
REJ09B0273-0500
Initial value:
* To prevent TCSR from being modified easily, the write method differs from that used for
* The overflow interval listed is the time from when the TCNT begins counting at H'00
Bit name:
Bit Name
Overflow flag (OVF)
Timer mode select
(WT/IT)
Timer enable (TME)
Clock select 2 to 0
(CKS2 to CKS0)
general registers. For details, see section 12.2.4, Register Access.
until an overflow occurs.
R/W:
Bit:
R/(W) *
OVF
7
0
WT/IT
R/W
6
0
Value
0
1
0
1
0
1
0
1
0
1
0
1
TME
R/W
5
0
0
1
0
1
0
1
0
1
[Clearing condition]
Read OVF, then write 0 in OVF
Interval timer mode: Interval timer interrupt (ITI)
request sent to CPU when TCNT overflows
externally when TCNT overflows
Clock
H'FFFF8610
Description
No TCNT overflow in interval timer mode
TCNT overflow in interval timer mode
Watchdog timer mode: WDTOVF signal output
Timer disabled: TCNT is initialized to H'00 and
halted
Timer enabled: TCNT starts counting
WDTOVF signal or interrupt generated when
TCNT overflows
/2 (Initial value)
/64
/128
/256
/512
/1024
/4096
/8192
—
R
4
1
—
R
3
1
CKS2
R/W
2
0
Overflow Interval *
(When
25.6 µs
819.2 µs
1.6 ms
3.3 ms
6.6 ms
13.1 ms
52.4 ms
104.9 ms
8
CKS1
R/W
(Initial value)
(Initial value)
(Initial value)
1
0
= 20 MHz)
CKS0
R/W
WDT
0
0