HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 110

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Interrupt Controller (INTC)
Rev. 5.00 Jan 06, 2006 page 90 of 818
REJ09B0273-0500
IRQOUT = high level*
Branches to exception
IRQOUT = low level*
Copy accept-interrupt
Notes: 1.
I3 to I0: Interrupt mask bits of status register
Save SR to stack
Save PC to stack
Reads exception
level to I3 to I0
service routine
execution state
vector table
Interrupt?
Program
NMI?
2.
Yes
Yes
IRQOUT is the same signal as the interrupt request signal to the CPU (see
figure 6.1). Thus, it is output when there is a higher priority interrupt request
than the one in the I3 to I0 bits of the SR.
When the accepted interrupt is sensed by edge, the IRQOUT pin becomes
high level at the point when the CPU starts interrupt exception processing
instead of instruction execution (before SR is saved to the stack).
If the interrupt controller has accepted another interrupt with a higher priority
and has output an interrupt request to the CPU, the IRQOUT pin will remain
low level.
User break?
1
No
No
2
Figure 6.3 Interrupt Sequence Flowchart
Yes
Yes
interrupt?
level 14?
I3 to I0
No
Level 15
No
Yes
Yes
No
interrupt?
level 13?
I3 to I0
Level 14
No
Yes
Yes
No
interrupt?
I3 to I0 =
level 0?
Level 1
Yes
No
No