HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 325

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HD64F7050

Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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10.3.17 Timing of Buffer Register (BFR) Write and Transfer by Buffer Function
In channels 6 to 9, if the BFR value is transferred to the duty register (DTR) by a compare-match
with the cycle register (CYLR) in the T2 state during a write cycle from the CPU to the buffer
register (BFR), the value prior to the CPU write to BFR is transferred to DTR.
The timing in this case is shown in figure 10.29. In this example, a CYLR compare-match and a
write of H'AAAA to BFR occur simultaneously when the BFR value is H'5555.
Figure 10.29 Contention between Buffer Register (BFR) Write and Transfer by Buffer
Compare-match signal
Internal write signal
Address
DTR
BFR
CK
H'5555
Function
BFR write cycle
T1
BFR address
Rev. 5.00 Jan 06, 2006 page 305 of 818
Section 10 Advanced Timer Unit (ATU)
H'AAAA
written
to BFR
T2
H'AAAA
H'5555
REJ09B0273-0500

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