HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 475

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HD64F7050

Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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14.4.5
The A/D0 converter module can be activated by an A/D conversion request from the ATU’s
channel 0 interval timer.
To activate the A/D converter by means of the ATU, set the TRGE bit to 1 in A/D control register
0 (ADCR0) and clear the EXTRG bit to 0 in the A/D trigger register (ADTRGR). When an ATU
channel 0 interval timer A/D conversion request is generated after these settings have been made,
the ADST bit set to 1. The timing from setting of the ADST bit until the start of A/D conversion is
the same as when 1 is written into the ADST bit by software.
14.4.6
When channel 15 is used in scan mode, the conversion timing can be monitored with the ADEND
output pin.
After the channel 15 analog voltage has been latched in scan mode, and conversion has started, the
ADEND pin goes high. The ADEND pin subsequently goes low when channel 15 conversion
ends.
State of channel 12
State of channel 13
State of channel 14
State of channel 15
A/D Converter Activation by ATU
ADEND Output Pin
ADEND
(AN12)
(AN13)
(AN14)
(AN15)
conversion
A/D
Idle
Idle
Figure 14.7 ADEND Output Timing
conversion
A/D
Idle
conversion
A/D
Idle
Idle
conversion
A/D
Rev. 5.00 Jan 06, 2006 page 455 of 818
Idle
conversion
A/D
Section 14 A/D Converter
conversion
A/D
REJ09B0273-0500
Idle
conversion
Idle
A/D
Idle

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