HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 393

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

13.2
13.2.1
The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into the
RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte
has been received, it is automatically transferred to the RDR.
The CPU cannot read or write the RSR directly.
13.2.2
The receive data register (RDR) stores serial receive data. The SCI completes the reception of one
byte of serial data by moving the received data from the receive shift register (RSR) into the RDR
for storage. The RSR is then ready to receive the next data. This double buffering allows the SCI
to receive data continuously.
The CPU can read but not write the RDR. The RDR is initialized to H'00 by a power-on reset, in
hardware standby mode and software standby mode.
Initial value:
Register Descriptions
Receive Shift Register (RSR)
Receive Data Register (RDR)
R/W:
R/W:
Bit:
Bit:
—
R
7
7
0
—
R
6
6
0
—
R
5
5
0
Section 13 Serial Communication Interface (SCI)
—
R
4
4
0
Rev. 5.00 Jan 06, 2006 page 373 of 818
—
R
3
3
0
—
R
2
2
0
REJ09B0273-0500
—
R
1
1
0
—
R
0
0
0