HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 171

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 9.2 is a flowchart of this procedure.
DMATCR – 1
(SAR, DAR, TCR, CHCR, DMAOR)
DEI interrupt request (when IE = 1)
Notes: 1.
NMIF, AE, TE = 0?
Transfer (1 transfer unit);
NMIF = 1, AE = 1,
DE, DME = 1 and
Transfer request
DE = 0, or DME
DMATCR = 0?
Initial settings
Transfer ends
Yes
Yes
Yes
occurs? *
Yes
2.
3.
Start
Does
= 0?
DMATCR, SAR and DAR
updated
In auto-request mode, transfer begins when NMIF, AE, and TE are all 0,
and the DE and DME bits are set to 1.
DREQ = level detection in burst mode (external request) or cycle-steal
mode.
DREQ = edge detection in burst mode (external request), or auto-request
mode in burst mode.
1
Figure 9.2 DMAC Transfer Flowchart
No
No
No
No
Section 9 Direct Memory Access Controller (DMAC)
NMIF = 1, AE = 1,
Transfer aborted
DE = 0, or DME
Normal end
Yes
*
Does
= 0?
3
Rev. 5.00 Jan 06, 2006 page 151 of 818
DREQ detection selection
transfer request mode,
Bus mode,
system
No
*
2
REJ09B0273-0500