HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 627

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the SH7051 measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The SH7051 calculates the bit rate
of the transmission from the host from the measured low period, and transmits one H'00 byte to
the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment
end indication (H'00) has been received normally, and transmit one H'55 byte to the SH7051. If
reception cannot be performed normally, initiate boot mode again (reset), and repeat the above
operations. Depending on the host’s transmission bit rate and the SH7051’s system clock
frequency, there will be a discrepancy between the bit rates of the host and the SH7051. To ensure
correct SCI operation, the host’s transfer bit rate should be set to 4800bps, 9600bps.
Table 19.6 shows host transfer bit rates and system clock frequencies for which automatic
adjustment of the SH7051 bit rate is possible. The boot program should be executed within this
system clock range.
Table 19.6 System Clock Frequencies for which Automatic Adjustment of SH7051 Bit Rate
Host Bit Rate
9600bps
4800bps
is Possible
Start
bit
D0
System Clock Frequency for which Automatic Adjustment
of SH7051 Bit Rate is Possible
8 to 20MHz
4 to 20MHz
Low period (9 bits) measured (H'00 data)
D1
D2
D3
D4
Rev. 5.00 Jan 06, 2006 page 607 of 818
D5
Section 19 ROM (256 kB Version)
D6
D7
(1 or more bits)
REJ09B0273-0500
High period
Stop
bit