HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 149

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read
other external spaces, or for this LSI, to do write accesses. In the same manner, IW21 and IW20
specify the number of idle cycles after a CS2 space read, IW11 and IW10, the number after a CS1
space read, and IW01 and IW00, the number after a CS0 space read.
DIW specifies the number of idle cycles required, after a DRAM space read either to read other
external spaces (CS space), or for this LSI, to do write accesses.
0 to 3 cycles can be specified for CS space, and 0 to 1 cycle for DRAM space.
Address
CSm
Data
WRx
CSn
RD
CK
CSn space read
T
1
Figure 8.7 Idle Cycle Insertion Example
T
2
Idle cycle
T
idle
Rev. 5.00 Jan 06, 2006 page 129 of 818
Section 8 Bus State Controller (BSC)
CSm space write
T
1
T
2
REJ09B0273-0500