HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 718

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Appendix A On-Chip Supporting Module Registers
Bit
4
3
2
1
0
Rev. 5.00 Jan 06, 2006 page 698 of 818
REJ09B0273-0500
Bit Name
Framing error
(FER)
Parity error (PER)
Transmit end
(TEND)
Multiprocessor bit
(MPB)
Multiprocessor bit
transfer (MPBT)
0
1
0
1
0
1
0
1
0
1
Value
Description
Receiving in progress, or completed normally
[Clearing conditions]
1. Power-on reset, or transition to hardware standby mode or software
2. Read FER when FER = 1, then write 0 in FER
Framing error occurred during reception
[Setting condition]
Framing error (stop bit is 0)
Receiving in progress, or completed normally
[Clearing conditions]
1. Power-on reset, or transition to hardware standby mode or software
2. Read PER when PER = 1, then write 0 in PER
Parity error occurred during reception
[Setting condition]
Parity error (parity of receive data does not match parity setting of O/E bit
in SMR)
Transmitting in progress
[Clearing conditions]
1. Read TDRE when TDRE = 1, then write 0 in TDRE
2. The DMAC writes data in TDR
Transmitting has ended
[Setting conditions]
1. Power-on reset, or transition to hardware standby mode or software
2. TE is cleared to 0 in SCR
3. TDRE = 1 when last bit of 1-byte serial transmit character is
Multiprocessor bit value in receive data is 0
Multiprocessor bit value in receive data is 1
Multiprocessor bit value in transmit data is 0
Multiprocessor bit value in transmit data is 1
standby mode
standby mode
standby mode
transmitted
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)