HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 439

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 13.19 shows an example of SCI transmit operation.
SCI serial transmission operates as follows.
1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes
2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts
If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads
4. After the end of serial transmission, the SCK pin is held in the high state.
zation clock
Synchroni-
Serial data
that the transmit data register (TDR) contains new data and loads this data from the TDR into
the transmit shift register (TSR).
transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the
SCI requests a transmit-data-empty interrupt (TxI) at this time.
clock source is selected, the SCI outputs data in synchronization with the input clock. Data are
output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7).
data from the TDR into the TSR, then begins serial transmission of the next frame. If TDRE is
1, the SCI sets the TEND bit in the SSR to 1, transmits the MSB, then holds the transmit data
pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in the SCR is set to
1, a transmit-end interrupt (TEI) is requested at this time.
TDRE
TEND
Transmit direction
request
TxI
Figure 13.19 Example of SCI Transmit Operation
Bit 0
LSB
clears TDRE to 0
data in TDR and
handler writes
TxI interrupt
Bit 1
1 frame
request
Section 13 Serial Communication Interface (SCI)
TxI
MSB
Bit 7
Rev. 5.00 Jan 06, 2006 page 419 of 818
Bit 0
Bit 1
REJ09B0273-0500
Bit 6
request
TEI
Bit 7