HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 251

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
TIOR4A and TIOR4B are 8-bit readable/writable registers. When bit 1 of TMDR is 0, they
specify whether general registers GR4A to GR4D are used as input capture or compare-match
registers, and also perform edge detection and output value setting. Also, when bit 1 of TMDR is
0, they select enabling or disabling of free-running counter (TCNT4) clearing.
Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
TIOR5A is an 8-bit readable/writable register. When bit 2 of TMDR is 0, it specifies whether
general registers GR5A and GR5B are used as input capture or compare-match registers, and also
performs edge detection and output value setting. Also, when bit 2 of TMDR is 0, TIOR5A selects
enabling or disabling of free-running counter (TCNT5) clearing.
TIOR5A is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Initial value:
Initial value:
Initial value:
TIOR4A
TIOR4B
TIOR5A
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
CCI4B
CCI4D
CCI5B
R/W
R/W
R/W
7
0
7
0
7
0
IO4D2
IO4B2
IO5B2
R/W
R/W
R/W
6
0
6
0
6
0
IO4D1
IO4B1
IO5B1
R/W
R/W
R/W
5
0
5
0
5
0
IO4D0
IO4B0
IO5B0
R/W
R/W
R/W
4
0
4
0
4
0
Rev. 5.00 Jan 06, 2006 page 231 of 818
Section 10 Advanced Timer Unit (ATU)
CCI4C
CCI4A
CCI5A
R/W
R/W
R/W
3
0
3
0
3
0
IO4C2
IO4A2
IO5A2
R/W
R/W
R/W
2
0
2
0
2
0
REJ09B0273-0500
IO4C1
IO4A1
IO5A1
R/W
R/W
R/W
1
0
1
0
1
0
IO4C0
IO4A0
IO5A0
R/W
R/W
R/W
0
0
0
0
0
0