HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 446

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Serial Communication Interface (SCI)
13.5
Sections 13.5.1 through 13.5.9 provide information for using the SCI.
13.5.1
The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data
from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can
be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is
0, however, the old data stored in TDR will be lost because the data has not yet been transferred to
the TSR. Before writing transmit data to the TDR, be sure to check that TDRE is set to 1.
13.5.2
Table 13.13 indicates the state of the SSR status flags when multiple receive errors occur
simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to the
RDR, so receive data is lost.
Table 13.13 SSR Status Flags and Transfer of Receive Data
Note: O = Receive data is transferred from RSR to RDR.
Rev. 5.00 Jan 06, 2006 page 426 of 818
REJ09B0273-0500
Receive Error Status
Overrun error
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error + parity
error
X = Receive data is not transferred from RSR to RDR.
Notes on Use
TDR Write and TDRE Flags
Simultaneous Multiple Receive Errors
RDRF
1
0
0
1
1
0
1
ORER
1
0
0
1
1
0
1
SSR Status Flags
FER
0
1
0
1
0
1
1
PER
0
0
1
0
1
1
1
Receive Data
Transfer
RSR
X
O
O
X
X
O
X
RDR