HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 640
HD64F7050
Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD64F7050.pdf
(841 pages)
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Section 19 ROM (256 kB Version)
Example in which Flash Memory Block Area (EB8) is Overlapped
1. Set bits RAMS, RAM1, and RAM0 in RAMER to 1, 0, 0, to overlap part of RAM onto the
2. Real-time programming is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB8).
Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks
Rev. 5.00 Jan 06, 2006 page 620 of 818
REJ09B0273-0500
area (EB8) for which real-time programming is required.
H'000000
H'03F000
H'03F400
H'03F800
H'03FC00
H'03FFFF
2. A RAM area cannot be erased by execution of software in accordance with the erase
regardless of the value of RAM1 and RAM0 (emulation protection). In this state,
setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), or the P2 or E2
bit in flash memory control register 2 (FLMCR2), will not cause a transition to
program mode or erase mode. When actually programming or erasing a flash memory
area, the RAMS bit should be cleared to 0.
algorithm while flash memory emulation in RAM is being used.
Figure 19.11 Example of RAM Overlap Operation
Flash memory
EB0 to EB7
EB8
EB9
EB10
EB11
This area can be accessed
from both the RAM area
and flash memory area
On-chip RAM
H'FFFFD800
H'FFFFDBFF
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