HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 211

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 9.9
When address reload is on, the SAR value returns to its initially established value every four
transfers. In the above example, when a transfer request is input from the A/D converter, the byte
size data is first read in from the H'FFFF85F0 register of AD1 and that data is written to the
internal address H'FFFFE800. Because a byte size transfer was performed, the SAR and DAR
values at this point are H'FFFF85F1 and H'FFFFE801, respectively. Also, because this is a burst
transfer, the bus rights remain secured, so continuous data transfer is possible.
When four transfers are completed, if the address reload is off, execution continues with the fifth
and sixth transfers and the SAR value continues to increment from H'FFFF85F3 to H'FFFF85F4 to
H'FFFF85F5 and so on. However, when the address reload is on, the DMAC transfer is halted
upon completion of the fourth one and the bus right request signal to the CPU is cleared. At this
time, the value stored in SAR is not H'FFFF85F3 to H'FFFF85F4, but H'FFFF85F3 to
H'FFFF85F0, a return to the initially established address. The DAR value always continues to be
decremented regardless of whether the address reload is on or off.
The DMAC internal status, due to the above operation after completion of the fourth transfer, is
indicated in Table 9.10 for both address reload on and off.
Transfer Conditions
Transfer source: on-chip A/D converter ch1 (AD1)
Transfer destination: internal memory
Transfer count: 128 times (reload count 32 times)
Transfer source address: incremented
Transfer destination address: incremented
Transfer request source: A/D converter (AD1)
Bus mode: burst
Transfer unit: byte
Interrupt request generation at end of transfer
Channel priority ranking: 0
Transfer Conditions and Register Set Values for Transfer between A/D
Converter and Internal Memory
2
3
1
Section 9 Direct Memory Access Controller (DMAC)
Rev. 5.00 Jan 06, 2006 page 191 of 818
SAR2
DAR2
CHCR2
Register
DMATCR2
DMAOR
H'FFFFE800
Value
H'FFFF85F0
H'00000080
H'00085F21
H'0101
REJ09B0273-0500