HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 436

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Serial Communication Interface (SCI)
shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and receive data register (RDR), which retain their previous contents.
Figure 13.17 is a sample flowchart for initializing the SCI.
1. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external
2. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE,
3. Select the communication format in the serial mode register (SMR).
4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the
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clock is used.
and RE cleared to 0.
serial control register (SCR) to 1. When selecting the simultaneous transmission and receiving,
set TE and RE bits to 1 simultaneously. Also set RIE, TIE, TEIE, and MPIE. The TxD, RxD
pins becomes usable in response to the PFC corresponding bits and the TE, RE bit settings.
Figure 13.17 Sample Flowchart for SCI Initialization
Set RIE, TIE, TEIE, and MPIE bits
Clear TE and RE bits to 0 in SCR
Set RIE, TIE, TEIE, MPIE, CKE1,
Set TE and RE to 1 in SCR;
Select transmit/receive
and CKE0 bits in SCR
1-bit interval elapsed?
Start of initialization
(TE and RE are 0)
Set value in BRR
format in SMR
End
Yes
Wait
No
1
2
3
4