HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 326

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HD64F7050

Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 10 Advanced Timer Unit (ATU)
10.4
The ATU has 44 interrupt sources of five kinds: input capture interrupts, compare-match
interrupts, overflow interrupts, underflow interrupts, and interval interrupts.
10.4.1
IMF (ICF) Setting Timing in Input Capture: When an input capture signal is generated, the
IMF bit (ICF bit in case of channel 0) is set to 1 in the timer status register (TSR), and the TCNT
value is simultaneously transferred to the corresponding GR (ICR in the case of channel 0).
The timing in this case is shown in figure 10.30.
In the example in figure 10.30, a signal is input from an external pin, and input capture is
performed on detection of a rising edge.
Rev. 5.00 Jan 06, 2006 page 306 of 818
REJ09B0273-0500
Interrupt request signal
Interrupts
Status Flag Setting Timing
Internal input capture
Interrupt status flag
Input capture input
Figure 10.30 IMF (ICF) Setting Timing in Input Capture
IMF (ICF)
GR (ICR)
IMI (ICI)
TCNT
signal
CK
t
TICS
N
(input capture input setup time)
N

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