HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 129
HD64F7050
Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD64F7050.pdf
(841 pages)
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8.1
The bus state controller (BSC) divides up the address spaces and outputs control for various types
of memory. This enables memories like SRAM, and ROM to be linked directly to the LSI without
external circuitry.
8.1.1
The BSC has the following features:
Address space is divided into four spaces
On-chip ROM and RAM interfaces
A maximum linear 2 Mbytes for on-chip ROM effective mode, and a maximum linear
4-Mbyte for on-chip ROM ineffective mode for address space CS0
A maximum linear 4 Mbytes for each of the address spaces CS1–CS3
Bus width can be selected for each space (8 or 16 bits)
Wait states can be inserted by software for each space
Wait state insertion with WAIT pin in external memory space access
Outputs control signals for each space according to the type of memory connected
On-chip RAM access of 32 bits in 1 state
Features
Overview
Section 8 Bus State Controller (BSC)
Rev. 5.00 Jan 06, 2006 page 109 of 818
Section 8 Bus State Controller (BSC)
REJ09B0273-0500
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