HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 349

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HD64F7050

Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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10.7
Note that the kinds of operation and contention described below occur during ATU operation.
Contention between TCNT Write and Clearing by Compare-Match: With channel 3 to 9 free-
running counters (TCNT3 to TCNT9), if a compare-match occurs in the T2 state of a CPU write
cycle when clearing is enabled, the write to TCNT has priority and clearing is not performed.
The compare-match remains valid, and writing of 1 to the interrupt status flag and waveform
output to an external destination are performed in the same way as for a normal compare-match.
The timing in this case is shown in figure 10.53.
Usage Notes
Compare-match signal
External output signal
Counter clear signal
Internal write signal
Interrupt status flag
Figure 10.53 Contention between TCNT Write and Clear
(1 output)
Address
TCNT
CK
TCNT address
T1
Rev. 5.00 Jan 06, 2006 page 329 of 818
Section 10 Advanced Timer Unit (ATU)
T2
CPU write value
REJ09B0273-0500

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