HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 380

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Watchdog Timer (WDT)
12.2.3
The RSTCSR is an 8-bit readable and writable register. (The RSTCSR differs from other registers
in that it is more difficult to write. See section 12.2.4, Register Access, for details.) It controls
output of the internal reset signal generated by timer counter (TCNT) overflow and selects the
internal reset signal type. RSTCR is initialized to H'1F by input of a reset signal from the RES pin,
but is not initialized by the internal reset signal generated by the overflow of the WDT. It is
initialized to H'1F in hardware standby mode and software standby mode.
Note:
Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that the TCNT has overflowed
(H'FF to H'00) in the watchdog timer mode. It is not set in the interval timer mode.
Bit 7: WOVF
0
1
Bit 6—Reset Enable (RSTE): Selects whether to reset the chip internally if the TCNT overflows
in the watchdog timer mode.
Bit 6: RSTE
0
1
Bit 5, 4—Reserved: These bits always read as 0. The write value should always be 0.
Bits 3 to 0—Reserved: These bits always read as 1. The write value should always be 1.
Rev. 5.00 Jan 06, 2006 page 360 of 818
REJ09B0273-0500
Initial value:
* Only 0 can be written in bit 7 to clear the flag.
Reset Control/Status Register (RSTCSR)
R/W:
Bit:
R/(W) *
WOVF
7
0
Description
No TCNT overflow in watchdog timer mode (initial value)
Cleared when software reads WOVF, then writes 0 in WOVF
Set by TCNT overflow in watchdog timer mode
Description
Not reset when TCNT overflows (initial value). LSI not reset internally,
but TCNT and TCSR reset within WDT.
Reset when TCNT overflows
RSTE
R/W
6
0
—
R
5
0
—
R
4
0
—
R
3
1
—
R
2
1
—
R
1
1
—
R
0
1