HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 238

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Advanced Timer Unit (ATU)
Bit 2—Counter Start 2 (STR2): Starts and stops free-running counter 2 (TCNT2).
Bit 2:
STR2
0
1
Bit 1—Counter Start 1 (STR1): Starts and stops free-running counter 1 (TCNT1).
Bit 1:
STR1
0
1
Bit 0—Counter Start 0 (STR0): Starts and stops free-running counter 0 (TCNT0).
Bit 0:
STR0
0
1
10.2.2
The timer mode register (TMDR) is an 8-bit register. The ATU has one TDR register.
TMDR is an 8-bit readable/writable register that specifies whether channels 3 to 5 are used in
input capture/output compare mode or PWM mode.
TMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Rev. 5.00 Jan 06, 2006 page 218 of 818
REJ09B0273-0500
Initial value:
Timer Mode Register (TMDR)
Description
TCNT2 is halted
TCNT2 counts
Description
TCNT1 is halted
TCNT1 counts
Description
TCNT0 is halted
TCNT0 counts
R/W:
Bit:
—
R
7
0
—
R
6
0
—
R
5
0
—
R
4
0
—
R
3
0
T5PWN T4PWN T3PWN
R/W
2
0
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
R/W
0
0