HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 120

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 User Break Controller (UBC)
7.2.3
User break bus cycle register (UBBR) is a 16-bit readable/writable register that selects from
among the following four break conditions:
1. CPU cycle/DMA cycle
2. Instruction fetch/data access
3. Read/write
4. Operand size (byte, word, longword)
UBBR is initialized by a power on reset to H'0000. It is not initialized in software standby mode.
Bits 15 to 8—Reserved: These bits always read as 0. The write value should always be 0.
Bits 7 and 6—CPU Cycle/Peripheral Cycle Select (CP1, CP0): These bits designate break
conditions for CPU cycles or peripheral cycles (DMA cycles).
Bit 7: CP1
0
1
Rev. 5.00 Jan 06, 2006 page 100 of 818
REJ09B0273-0500
Initial value:
Initial value:
User Break Bus Cycle Register (UBBR)
R/W:
R/W:
Bit:
Bit:
Bit 6: CP0
0
1
0
1
CP1
R/W
15
—
R
0
7
0
CP0
R/W
14
—
R
0
6
0
Description
No user break interrupt occurs (initial value)
Break on CPU cycles
Break on peripheral cycles
Break on both CPU and peripheral cycles
R/W
ID1
13
—
R
0
5
0
R/W
ID0
12
—
R
0
4
0
RW1
R/W
11
—
R
0
3
0
RW0
R/W
10
—
R
0
2
0
R/W
SZ1
—
R
9
0
1
0
R/W
SZ0
—
R
8
0
0
0