HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 419
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HD64F7050
Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD64F7050.pdf
(841 pages)
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Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for
transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the
flowchart):
1. SCI initialization: Set the TxD pin using the PFC.
2. SCI status check and transmit data write: Read the serial status register (SSR), check that the
3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it
4. To output a break at the end of serial transmission, first clear the port data register (DR) to 0,
TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE
to 0.
reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a
transmit-data-empty interrupt request (TxI) in order to write data in TDR, the TDRE bit is
checked and cleared automatically.
then clear the TE to 0 in SCR and use the PFC to establish the TxD pin as an output port.
Figure 13.4 Sample Flowchart for SCI Initialization
Select transmit/receive format in SMR
Set TE or RE to 1 in SCR; Set RIE,
TIE, TEIE, and MPIE as necessary
Clear TE and RE bits to 0 in SCR
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0)
1-bit interval elapsed?
Set value to BRR
Initialize
End
Yes
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 06, 2006 page 399 of 818
No
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REJ09B0273-0500
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