HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 276

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Advanced Timer Unit (ATU)
Bit 1—Input Capture/Compare-Match Interrupt Enable (IME1B): Enables or disables
interrupt requests by IMF1B in TSR when IMF1B is set to 1.
Bit 1:
IME1B
0
1
Bit 0—Input Capture/Compare-Match Interrupt Enable (IME1A): Enables or disables
interrupt requests by IMF1A in TSR when IMF1A is set to 1.
Bit 0:
IME1A
0
1
Timer Interrupt Enable Register C (TIERC)
TIERC controls enabling/disabling of channel 2 input capture, compare-match, and overflow
interrupt requests.
Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2—Overflow Interrupt Enable (OVE2): Enables or disables interrupt requests by OVF2 in
TSR when OVF2 is set to 1.
Bit 2:
OVE2
0
1
Rev. 5.00 Jan 06, 2006 page 256 of 818
REJ09B0273-0500
Initial value:
Description
IMI1B interrupt requested by IMF1B is disabled
IMI1B interrupt requested by IMF1B is enabled
Description
IMI1A interrupt requested by IMF1A is disabled
IMI1A interrupt requested by IMF1A is enabled
Description
OVI2 interrupt requested by OVF2 is disabled
OVI2 interrupt requested by OVF2 is enabled
R/W:
Bit:
—
R
7
0
—
R
6
0
—
R
5
0
—
R
4
0
—
R
3
0
OVE2
R/W
2
0
IME2B
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
IME2A
R/W
0
0