HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 163

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

9.2.4
DMA channel control registers 0–3 (CHCR0–CHCR3) is a 32-bit read/write register where the
operation and transmission of each channel is designated. Bits 31–21 and bit 7 should always read
0. The written value should also be 0. They are initialized to 0 by a power-on reset and in standby
mode.
Notes: 1. TE bit: Allows only 0 write after reading 1.
Bit 20—Direct/Indirect (DI): Specifies either direct address mode operation or indirect address
mode operation for channel 3 source address. This bit is valid only in CHCR3. It always reads 0
for CHCR0–CHCR2, and cannot be modified.
Bit 20: DI
0
1
Initial value:
Initial value:
Initial value:
Initial value:
2. The DI, RO, RL, AM, AL, or DS bit may be absent, depending on the channel.
DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Description
Direct access mode operation for channel 3 (initial value)
Indirect access mode operation for channel 3
DM1
R/W
31
23
15
—
—
—
R
R
R
0
0
0
7
0
DM0
R/W
R/W
DS
30
22
14
—
—
R
R
0
0
0
6
0
SM1
R/W
R/W
TM
29
21
13
—
—
R
R
0
0
0
5
0
Section 9 Direct Memory Access Controller (DMAC)
R/W
SM0
R/W
R/W
TS1
28
20
12
—
DI
R
0
0
0
4
0
Rev. 5.00 Jan 06, 2006 page 143 of 818
R/W
R/W
R/W
RS3
TS0
RO
27
19
11
—
R
0
0
0
3
0
R/W
RS2
R/W
R/W
RL
26
18
10
—
IE
R
0
0
0
2
0
REJ09B0273-0500
R/(W) *
R/W
RS1
R/W
AM
TE
25
17
—
R
0
0
9
0
1
0
R/W
RS0
R/W
R/W
DE
AL
24
16
—
R
0
0
8
0
0
0