HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 465

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HD64F7050

Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Bits 1 and 0—Channel Select 1 and 0 (CH1 and CH0): These bits, together with the SCAN bit,
select the analog input channels.
To prevent incorrect operation, ensure that the ADST bit in A/D control/status register 1
(ADCSR1) is cleared to 0 before changing the analog input channel selection.
14.2.5
A/D control register 1 (ADCR1) is an 8-bit readable/writable register that controls the start of A/D
conversion and selects the operating clock.
ADCR1 is initialized to H'7F by a power-on reset, and in hardware standby mode and software
standby mode.
Bit 7—Trigger Enable (TRGE): Same as TRGE in ADCR0.
Bits 6 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
Bit 1:
CH3
0
1
Initial value:
A/D Control Register 1 (ADCR1)
Bit 0:
CH0
0
1
0
1
R/W:
Bit:
TRGE
R/W
7
0
AN12
AN13
AN14
AN15
Single Mode
R
6
1
(Initial value)
R
5
1
Analog Input Channels
R
4
1
Rev. 5.00 Jan 06, 2006 page 445 of 818
Scan Mode
AN12
AN12, 13
AN12–14
AN12–15
R
3
1
Section 14 A/D Converter
R
2
1
REJ09B0273-0500
R
1
1
R
0
1

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