HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 636

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 ROM (256 kB Version)
19.8.2
Software protection can be implemented by setting erase block register 1 (EBR1), erase block
register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software
protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), or
the P2 or E2 bit in flash memory control register 2 (FLMCR2), does not cause a transition to
program mode or erase mode. (See table 19.8.)
Table 19.8 Software Protection
Item
SWE pin protection
Block specification
protection
Emulation protection
Rev. 5.00 Jan 06, 2006 page 616 of 818
REJ09B0273-0500
Software Protection
Description
Clearing the SWE bit to 0 in FLMCR1 sets
the program/erase-protected state for all
blocks.
(Execute in on-chip RAM or external
memory.)
Erase protection can be set for individual
blocks by settings in erase block register 1
(EBR1) and erase block register 2
(EBR2).
Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-protected state.
Setting the RAMS bit to 1 in the RAM
emulation register (RAMER) places all
blocks in the program/erase-protected
state.
Program
Yes
—
Yes
Functions
Erase
Yes
Yes
Yes