HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 679

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HD64F7050

Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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22.3.2
Table 22.5 Control Signal Timing
Conditions: V
Note:
Item
RES pulse width
RES setup time
NMI setup time *
IRQ7–IRQ0 setup time (edge detection) *
IRQ7–IRQ0 setup time (level detection) *
NMI hold time
IRQ7–IRQ0 hold time
IRQOUT hold time
Bus request setup time
Bus acknowledge delay time 1
Bus acknowledge delay time 2
Bus three-state delay time
* The RES, NMI, and IRQ7–IRQ0 signals are asynchronous inputs, but when the setup
RES
CK
Control Signal Timing
times shown here are provided, the signals are considered to have produced changes
at clock fall. If the setup times are not provided, recognition is delayed until the next
clock rise or fall.
Ta = –40 to +85°C
CC
= 5.0 V
10%, AV
Figure 22.4 Reset Input Timing
V
CC
IH
= 5.0 V
t
RESS
V
IL
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
RESW
RESS
NMIS
IRQES
IRQLS
NMIH
IRQEH
IRQOD
BRQS
BACKD1
BACKD2
BZD
10%, AV
t
RESW
Rev. 5.00 Jan 06, 2006 page 659 of 818
ref
= 4.5 V to AV
Min
20
30
30
30
30
50
30
30
V
Section 22 Electrical Characteristics
IL
t
RESS
V
Max
25
25
25
50
IH
CC
, V
Unit
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
REJ09B0273-0500
SS
= AV
Figure
22.4
22.4, 22.5
22.5
22.6
22.7
SS
= 0 V,

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