HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 115

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

7.1
The user break controller (UBC) provides functions that simplify program debugging. Break
conditions are set in the UBC and a user break interrupt is generated according to the conditions of
the bus cycle generated by the CPU, DMAC, or DTC. This function makes it easy to design an
effective self-monitoring debugger, enabling the chip to easily debug programs without using a
large in-circuit emulator.
7.1.1
The features of the user break controller are:
Break compare conditions can be set:
User break interrupt generated upon satisfying break conditions. A user-designed user break
interrupt exception processing routine can be run.
Select either to break in the CPU instruction fetch cycle before the instruction is executed or
after.
Address
CPU cycle/DMA cycle
Instruction fetch or data access
Read or write
Operand size: byte/word/longword
Features
Overview
Section 7 User Break Controller (UBC)
Rev. 5.00 Jan 06, 2006 page 95 of 818
Section 7 User Break Controller (UBC)
REJ09B0273-0500