HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 157

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HD64F7050

Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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9.1.2
Figure 9.1 is a block diagram of the DMAC.
acknowledge)
A/D converter 0, 1
On-chip ROM
On-chip RAM
External I/O
External I/O
DREQ0, DREQ1
DACK0, DACK1
DRAK0, DRAK1
peripheral
(memory
mapped)
External
External
On-chip
module
ROM
RAM
(with
Block Diagram
SCI0–SCI2
DEIn
ATU
Figure 9.1 DMAC Block Diagram
Bus state
controller
Section 9 Direct Memory Access Controller (DMAC)
DMATCRn:
Bus interface
DMAOR:
CHCRn:
Activation
DARn:
SARn:
Register
Request
control
control
control
priority
control
Circuit
n:
Rev. 5.00 Jan 06, 2006 page 137 of 818
DMAC source address register
DMAC destination address register
DMAC transfer count register
DMAC channel control register
DMAC operation register
0, 1, 2, 3
DMAC module
DMATCRn
DMAOR
CHCRn
DARn
SARn
REJ09B0273-0500

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