HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 344
HD64F7050
Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD64F7050.pdf
(841 pages)
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Section 10 Advanced Timer Unit (ATU)
Sample Setup Procedure for Interval Timer Operation: An example of the setup procedure for
interval timer operation is shown in figure 10.50.
1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1).
2. Set the ITVE0–ITVE3 bit to be used in the interval interrupt request register (ITVRR) to 1. An
3. Set bit 0 to 1 in the timer start register (TSTR) to start TCNT0.
Note: TCNT0 bit 10 corresponds to ITVE0 and ITVAD0, bit 11 to ITVE1 and ITVAD1, bit 12
Rev. 5.00 Jan 06, 2006 page 324 of 818
REJ09B0273-0500
interrupt request can be sent to the CPU when the corresponding bit changes to 1 in the
channel 0 free-running counter (TCNT0).
To start A/D converter sampling, set the ITVAD0–ITVAD3 bit to be used in ITVRR to 1.
to ITVE2 and ITVAD2, and bit 13 to ITVE3 and ITVAD3.
Figure 10.50 Sample Setup Procedure for Interval Timer Operation
or start of A/D0 sampling
Interrupt request to CPU
Select counter clock
Start counter
Set interval
Start
1
2
3
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