HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 360

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Advanced Timer Unit (ATU)
Contention between DSTR Bit Setting by CPU and Clearing by Underflow: If underflow
occurs in the T2 state of a down-counter start register (DSTR) “1” write cycle by the CPU,
clearing to 0 by the underflow has priority, and the corresponding bit of DSTR is not set to 1.
The timing in this case is shown in figure 10.64.
Rev. 5.00 Jan 06, 2006 page 340 of 818
REJ09B0273-0500
Figure 10.64 Contention between DSTR Bit Setting by CPU and Clearing by Underflow
Internal write signal
Down-count start
Underflow signal
Address
register
DCNT
CK
0001
STR write cycle
DSTR address
T1
0000
1 written
to DSTR
T2
0000