HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 64

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
Instruction
SUB
SUBC
SUBV
Note:
Table 2.14 Logic Operation Instructions
Instruction
AND
AND
AND.B #imm,@(R0,GBR)
NOT
OR
OR
OR.B
TAS.B @Rn
TST
TST
TST.B #imm,@(R0,GBR)
XOR
XOR
XOR.B #imm,@(R0,GBR)
Note:
Rev. 5.00 Jan 06, 2006 page 44 of 818
REJ09B0273-0500
* The normal minimum number of execution cycles. (The number in parentheses is the
Rm,Rn
#imm,R0
Rm,Rn
Rm,Rn
#imm,R0
#imm,@(R0,GBR)
Rm,Rn
#imm,R0
Rm,Rn
#imm,R0
* The on-chip DMAC bus cycles are not inserted between the read and write cycles of
Rm,Rn
Rm,Rn
Rm,Rn
number of cycles when there is contention with following instructions.)
TAS instruction execution. However, bus release due to BREQ is carried out.
Instruction Code
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
Instruction Code
0010nnnnmmmm1001
11001001iiiiiiii
11001101iiiiiiii
0110nnnnmmmm0111
0010nnnnmmmm1011
11001011iiiiiiii
11001111iiiiiiii
0100nnnn00011011
0010nnnnmmmm1000
11001000iiiiiiii
11001100iiiiiiii
0010nnnnmmmm1010
11001010iiiiiiii
11001110iiiiiiii
Operation
Rn–Rm
Rn–Rm–T
Borrow
Rn–Rm
Underflow
Operation
Rn & Rm
R0 & imm
(R0 + GBR) & imm
(R0 + GBR)
~Rm
Rn | Rm
R0 | imm
(R0 + GBR) | imm
(R0 + GBR)
If (Rn) is 0, 1
MSB of (Rn) *
Rn & Rm; if the result is
0, 1
R0 & imm; if the result is
0, 1
(R0 + GBR) & imm; if
the result is 0, 1
Rn ^ Rm
R0 ^ imm
(R0 + GBR) ^ imm
(R0 + GBR)
T
Rn
Rn,
T
T
T
Rn,
Rn
Rn
Rn
R0
Rn
R0
R0
T; 1
T
Execu-
tion
Cycles
1
1
1
Execu-
tion
Cycles
1
1
3
1
1
1
3
4
1
1
3
1
1
3
T Bit
—
Borrow
Overflow
T Bit
—
—
—
—
—
—
—
Test
result
Test
result
Test
result
Test
result
—
—
—