HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 121

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Bits 5 and 4—Instruction Fetch/Data Access Select (ID1, ID0): These bits select whether to
break on instruction fetch and/or data access cycles.
Bits 3 and 2—Read/Write Select (RW1, RW0): These bits select whether to break on read
and/or write cycles.
Bits 1 and 0—Operand Size Select (SZ1, SZ0): These bits select operand size as a break
condition.
Note: When breaking on an instruction fetch, set the SZ0 bit to 0. All instructions are considered
Bit 5: ID1
0
1
Bit 3: RW1
0
1
Bit 1: SZ1
0
1
to be word-size accesses (even when there are instructions in on-chip memory and 2
instruction fetches are done simultaneously in 1 bus cycle).
Operand size is word for instructions or determined by the operand size specified for the
CPU/DMAC data access. It is not determined by the bus width of the space being
accessed.
Bit 4: ID0
0
1
0
1
Bit 2: RW0
0
1
0
1
Bit 0: SZ0
0
1
0
1
No user break interrupt occurs (initial value)
Break on instruction fetch cycles
Break on data access cycles
Break on both instruction fetch and data access cycles
No user break interrupt occurs (initial value)
Break on read cycles
Break on write cycles
Break on both read and write cycles
Operand size is not a break condition (initial value)
Break on byte access
Break on word access
Break on longword access
Description
Description
Description
Rev. 5.00 Jan 06, 2006 page 101 of 818
Section 7 User Break Controller (UBC)
REJ09B0273-0500