HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 256

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HD64F7050

Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 10 Advanced Timer Unit (ATU)
Timer Status Registers AH and AL (TSRAH, TSRAL)
TSRAH indicates the status of channel 0 interval interrupts.
Note:
Bits 7 to 4—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 3—Interval Interrupt Flag (IIF3): Status flag that indicates the generation of an interval
interrupt.
Bit 3:
IIF3
0
1
Bit 2—Interval Interrupt Flag (IIF2): Status flag that indicates the generation of an interval
interrupt.
Bit 2:
IIF2
0
1
Rev. 5.00 Jan 06, 2006 page 236 of 818
REJ09B0273-0500
Initial value:
* Only 0 can be written, to clear the flag.
Description
[Clearing condition]
When IIF3 is read while set to 1, then 0 is written in IIF3
[Setting condition]
When 1 is generated by AND of ITVE3 in ITVRR and bit 13 of TCNT0L
Description
[Clearing condition]
When IIF2 is read while set to 1, then 0 is written in IIF2
[Setting condition]
When 1 is generated by AND of ITVE2 in ITVRR and bit 12 of TCNT0L
R/W:
Bit:
R
7
0
R
6
0
R
5
0
R
4
0
R/(W) *
IIF3
3
0
R/(W) *
IIF2
2
0
R/(W) *
IIF1
1
0
(Initial value)
(Initial value)
R/(W) *
IIF0
0
0

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