HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 540

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 I/O Ports (I/O)
17.3.1
The port B register is shown in table 17.3.
Table 17.3 Port B Register
Name
Port B data register
Note: A register access is performed in two cycles regardless of the access size.
17.3.2
The port B data register (PBDR) is a 16-bit readable/writable register that stores port B data. Bits
PB11DR to PB0DR correspond to pins PB11/A21/POD to PB0/TO6.
When a pin functions as a general output, if a value is written to PBDR, that value is output
directly from the pin, and if PBDR is read, the register value is returned directly regardless of the
pin state. For PB6 to PB10, when the POD pin is driven low, general outputs go to the high-
impedance state regardless of the PBDR value. When the POD pin is driven high, the written
value is output from the pin.
When a pin functions as a general input, if PBDR is read the pin state, not the register value, is
returned directly. If a value is written to PBDR, although that value is written into PBDR it does
not affect the pin state. Table 17.4 summarizes port B data register read/write operations.
PBDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode or sleep mode.
Rev. 5.00 Jan 06, 2006 page 520 of 818
REJ09B0273-0500
Initial value:
R/W:
Bit:
Register Configuration
Port B Data Register (PBDR)
15
—
R
1
14
—
R
1
PB11
R/W R/W R/W R/W R/W R/W
DR
13
0
Abbreviation
PBDR
PB10
DR
12
0
PB9
DR
11
0
PB8
DR
10
0
R/W
R/W
PB7
DR
9
0
PB6
DR
8
0
Initial Value
H'C0C0
—
R
7
1
—
R
6
1
R/W R/W R/W R/W R/W R/W
PB5
DR
5
0
Address
H'FFFF8386
PB4
DR
4
0
PB3
DR
3
0
PB2
DR
2
0
Access Size
8, 16
PB1
DR
1
0
PB0
DR
0
0