HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 139
HD64F7050
Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD64F7050.pdf
(841 pages)
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- Current page: 139 of 841
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8.2.3
WCR1 is a 16-bit read/write register that specifies the number of wait cycles (0–15) for each CS
space.
WCR1 is initialized by a power-on reset and in hardware standby mode to H'FFFF. It is not
initialized by software standby mode.
Bits 15–12—CS3 Space Wait Specification (W33, W32, W31, W30): Specifies the number of
waits for CS3 space access.
Bit 3: SW3
0
1
Bit 2: SW2
0
1
Bit 1: SW1
0
1
Bit 0: SW0
0
1
Initial value:
Initial value:
Wait Control Register 1 (WCR1)
R/W:
R/W:
Bit:
Bit:
W33
W13
R/W
R/W
15
1
7
1
Description
No CS3 space CS assert extension
CS3 space CS assert extension (initial value)
Description
No CS2 space CS assert extension
CS2 space CS assert extension (initial value)
Description
No CS1 space CS assert extension
CS1 space CS assert extension (initial value)
Description
No CS0 space CS assert extension
CS0 space CS assert extension (initial value)
W32
W12
R/W
R/W
14
1
6
1
W31
W11
R/W
R/W
13
1
5
1
W30
W10
R/W
R/W
12
1
4
1
Rev. 5.00 Jan 06, 2006 page 119 of 818
Section 8 Bus State Controller (BSC)
W23
W03
R/W
R/W
11
1
3
1
W22
W02
R/W
R/W
10
1
2
1
REJ09B0273-0500
W21
W01
R/W
R/W
9
1
1
1
W20
W00
R/W
R/W
8
1
0
1
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