HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 486
HD64F7050
Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD64F7050.pdf
(841 pages)
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Section 15 Compare Match Timer (CMT)
15.3.2
One of four clocks ( /8, /32, /128, /512) obtained by dividing the system clock (CK) can be
selected by the CKS1, CKS0 bits of the CMCSR. Figure 15.3 shows the timing.
15.4
15.4.1
The CMT has a compare match interrupt for each channel, with independent vector addresses
allocated to each of them. The corresponding interrupt request is output when the interrupt request
flag CMF is set to 1 and the interrupt enable bit CMIE has also been set to 1.
When activating CPU interrupts by interrupt request, the priority between the channels can be
changed by using the interrupt controller settings. See section 6, Interrupt Controller, for details.
Rev. 5.00 Jan 06, 2006 page 466 of 818
REJ09B0273-0500
CMCNT input
Internal clock
CMCNT
CMCNT Count Timing
Interrupts
Interrupt Sources and DTC Activation
clock
CK
CMCOR
H'0000
CMCNT value
N – 1
Figure 15.2 Counter Operation
Figure 15.3 Count Timing
Counter cleared by
CMCOR compare match
N
Time
N + 1
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